Damascene process of rram top electrodes

ABSTRACT

A method is provided for manufacturing a memory. An insulating layer is formed over an array of interlayer conductors, and etched to define a first opening corresponding to a first interlayer conductor in the array, where the etching stops at a first top surface of the first interlayer conductor. A metal oxide layer is formed on the first top surface. A first layer of barrier material is deposited conformal with and contacting the metal oxide layer and surfaces of the first opening. Subsequently the insulating layer is etched to define a second opening corresponding to a second interlayer conductor in the array, where the etching stops at a second top surface of the second interlayer conductor. A second layer of barrier material is deposited conformal with and contacting the first layer of barrier material in the first opening. The first opening is filled with a conductive material.

BACKGROUND

1. Field of the Technology

The present invention relates to metal oxide based memory devices andmethods for manufacturing such devices.

2. Description of Related Art

Resistive random access memory, RRAM, is a type of nonvolatile memorythat provides the benefits of small cell size, scalability, ultrafastoperation, low-power operation, high endurance, good retention, largeOn/Off ratio, and CMOS compatibility. One type of RRAM includes metaloxide layers that can be caused to change resistance between two or morestable resistance ranges by application of electrical pulses at levelssuitable for implementation in integrated circuits.

As integrated circuit manufacturing technology scales down, damasceneprocess for forming top electrodes of RRAM cells becomes more suitablethan line patterning. A RRAM cell can include an access device that hasfirst and second terminals, a first plug that contacts the firstterminal, and a second plug that contacts the second terminal. Theaccess device can be a transistor or a diode. A metal oxide layercontacts a top surface of the first plug and acts as a memory element ina RRAM cell. An insulating layer is disposed over the first and secondplugs, and has first and second openings corresponding to the first andsecond plugs. First and second top electrodes can be disposed in thefirst and second openings, and connected to a bit line and a sourceline, respectively.

In methods of manufacturing RRAM cells, for example, top surfaces offirst and second plugs are oxidized to form a metal oxide layer beforerespective top electrodes are formed in the openings. The metal oxidelayer at the top surface of the second plug is to be etched away, as thesecond plug is designed to electrically connect the second terminal ofthe access device to a source line. However, etching away the metaloxide layer at the top surface of the second plug in the second openingcan cause damage to the second plug, leading to higher resistance in thesecond plug. Further, there can be contamination to side walls of thesecond opening in the insulating layer. For instance, if the second plugincludes copper (Cu) and the metal oxide layer includes a copper oxide(CuOx), copper may be sputtered onto side walls of the second openingwhile the metal oxide layer is etched away in the second opening.

In addition, a photoresist mask is used to protect the metal oxide layerin the first opening while the metal oxide layer is etched away in thesecond opening. After etching, the photoresist mask is stripped and thisstripping may damage the metal oxide layer in the first opening.

It is therefore desirable to provide a memory cell and method ofmanufacture that eliminates the possibility of damage to the plugconnected to the source line caused by etching away the metal oxidelayer, and the possibility of damage caused by photoresist stripping tothe metal oxide layer that acts as a programmable resistance element, inorder to provide a cost-effective method of manufacture.

SUMMARY

A method is provided for manufacturing a memory. A first opening isdefined corresponding to a first interlayer conductor (also referred toas a plug), a metal oxide layer is formed on a top surface of the firstinterlayer conductor in the first opening, and a first layer of barriermaterial is deposited in the first opening, before a second opening isdefined corresponding to a second interlayer conductor. Consequently,the method eliminates the possibility of damage to the second interlayerconnector caused by etching away the metal oxide layer in the secondopening, the possibility of contamination to side walls of the secondopening in the insulating layer caused by etching away the metal oxidelayer in the second opening, and the possibility of damage to the metaloxide layer in the first opening caused by photoresist stripping, asdescribed in the related art.

In implementations, an insulating layer is formed over an array ofinterlayer conductors. The insulating layer is etched to define a firstopening corresponding to a first interlayer conductor in the array,where the etching stops at a first top surface of the first interlayerconductor. A metal oxide layer is formed on the first top surface of thefirst interlayer conductor in the first opening. A diffusion barrierlayer can be formed between top surfaces of the array of interlayerconductors and the insulating layer, and contacting the top surfaces, toprevent diffusion from the interlayer conductors and to stop etching ofthe first opening and the second opening at top surfaces of the array ofinterlayer conductors. A first layer of barrier material is depositedconformal with and contacting the metal oxide layer on the firstinterlayer conductor and surfaces of the first opening. The first layerof barrier material can protect the metal oxide layer from potentialdamage by subsequent manufacturing steps to form and then remove etchmasks over the metal oxide layer, thus providing better interfacebetween the metal oxide layer and the top electrode. The first openingcan have a width greater than a width of the first interlayer connector.Subsequent to depositing the first layer of barrier material, theinsulating layer is etched to define a second opening corresponding to asecond interlayer conductor in the array, where the etching stops at asecond top surface of the second interlayer conductor. A second layer ofbarrier material is deposited conformal with and contacting the firstlayer of barrier material in the first opening. The first opening isfilled with a conductive material. The first and second interlayerconductors are connected to first and second terminals of an accessdevice respectively.

When etching to define the first opening, a first etch mask can be usedover the insulating layer, where the first etch mask has a mask regioncorresponding to the second opening and a spaced apart regioncorresponding to the first opening. When etching to define the secondopening, a second etch mask can be used over the insulating layer, wherethe second etch mask has a mask region corresponding to the firstopening and a spaced apart region corresponding to the second opening.

The second layer of barrier material can be deposited conformal with andcontacting the second top surface of the second interlayer conductor inthe second opening and surfaces of the second opening, and the secondopening can be filled with the conductive material, where a layercomprised of a metal oxide is not present between the second top surfaceand the second layer of barrier material.

A first access line electrically connected to the metal oxide layer canbe formed, and can act as a bit line. A second access line electricallyconnected to the second interlayer conductor can be formed, and can actas a source line.

An array of access devices coupled to the array of interlayer conductorscan be formed, where the array includes the first mentioned accessdevice. The first mentioned access device can include a diode or atransistor. In an embodiment where the first mentioned access deviceincludes a transistor, a third access line electrically connected to agate terminal of the transistor can be formed.

The metal oxide layer can be characterized by having a programmableresistance. The first interlayer connector can consist essentially of ametal, and the metal oxide layer can include an oxide of the metal. Thefirst interlayer connector can consist essentially of a transitionmetal, and the metal oxide layer can include an oxide of the transitionmetal.

Other aspects and advantages of the present technology can be seen onreview of the drawings, the detailed description and the claims, whichfollow.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a cross-sectional view of a memory cell in accordancewith an embodiment.

FIGS. 2 through 8 illustrate example steps in manufacturing a memorycell as shown in FIG. 1.

FIG. 9 shows a circuit diagram of a RRAM (Resistive random accessmemory) array in accordance with an embodiment.

FIG. 10 illustrates a simplified layout diagram of memory cells inaccordance with the embodiment shown in FIG. 9.

FIG. 11 shows a circuit diagram of a RRAM array in accordance with asecond embodiment.

FIG. 12 illustrates a simplified layout diagram of memory cells inaccordance with the second embodiment shown in FIG. 11.

FIG. 13 shows a circuit diagram of a RRAM array in accordance with athird embodiment.

FIG. 14 illustrates a simplified layout diagram of memory cells inaccordance with the third embodiment shown in FIG. 13.

FIG. 15 shows a circuit diagram of a RRAM array in accordance with anembodiment using diodes as access devices.

FIG. 16 illustrates a simplified layout diagram of memory cells inaccordance with the embodiment using diodes as access devices shown inFIG. 15.

FIG. 17 illustrates a simplified flowchart of an embodiment of a methodfor manufacturing a memory device.

DETAILED DESCRIPTION

A detailed description of embodiments of the present technology isprovided with reference to the Figures. It is to be understood thatthere is no intention to limit the technology to the specificallydisclosed structural embodiments and methods but that the technology maybe practiced using other features, elements, methods and embodiments.Preferred embodiments are described to illustrate the presenttechnology, not to limit its scope, which is defined by the claims.Those of ordinary skill in the art will recognize a variety ofequivalent variations on the description that follows. Like elements invarious embodiments are commonly referred to with like referencenumerals.

FIG. 1 illustrates a cross-sectional view of a memory cell (e.g. 100) inaccordance with an embodiment. A patterned insulating layer (e.g. 150)is disposed over an array of interlayer conductors (e.g. 131, 132). Thepatterned insulating layer (e.g. 150) includes a first opening (e.g.161) corresponding to a first interlayer conductor (e.g. 131) in thearray, and a second opening (e.g. 162) corresponding to a secondinterlayer conductor (e.g. 132) in the array. The first opening and thesecond opening extend through the patterned insulating layer, and stopat a first top surface (e.g. 131T) of the first interlayer conductor(e.g. 131) and a second top surface (e.g. 132T) of the second interlayerconductor (e.g. 132), respectively.

The first and second interlayer conductors (e.g. 131, 132) are comprisedof electrically conductive elements. The interlayer conductors may becomprised of, for example, one or more elements selected from the groupconsisting of Ti, W, Mo, Al, Hf, Ta, Cu, Pt, It, La, Ni, N, O, and Ru,and combinations thereof, and in some embodiments may comprise more thanone layer. In one implementation, the first and second interlayerconductors can consist essentially of a metal, and the metal oxide layercan comprise an oxide of the metal. In another implementation, the firstand second interlayer conductors can consist essentially of a transitionmetal, and the metal oxide layer can comprise an oxide of the transitionmetal.

A metal oxide layer (e.g. 170) is disposed on the first top surface(e.g. 131T) of the first interlayer conductor (e.g. 131), while a layercomprised of a metal oxide is not present on the second top surface(e.g. 132T) of the second interlayer conductor (e.g. 132). The metaloxide layer can be characterized by having a programmable resistance sothat the metal oxide layer is programmable to at least two resistancestates. For instance, the metal oxide layer may comprise one or moretungsten-oxygen compounds (WOx), such as one or more of WO₃, W₂O₅, WO₂.The metal oxide layer can have a graded profile including WO₃, W₂O₅ andWO₂ such that the oxygen ratio in the metal oxide layer decreases fromthe first opening (e.g. 161) towards the first interlayer conductor(e.g. 131).

In the embodiment shown, the metal oxide layer 170 can be a single layerformed by oxidizing the top surface of the first interlayer conductor131 and therefore is self-aligned with the first interlayer conductor131. The metal oxide layer can extrude from the first top surface of thefirst interlayer conductor into the first opening due to volumeexpansion during forming the metal oxide layer. In alternativeembodiments, the metal oxide layer 170 may comprise other metal oxides,for example a metal oxide from the group of nickel oxide, aluminumoxide, magnesium oxide, cobalt oxide, titanium oxide, titanium-nickeloxide, zirconium oxide, and copper oxide.

A diffusion barrier layer (e.g. 140) can be disposed between topsurfaces of the array of interlayer conductors and the patternedinsulating layer. The diffusion barrier layer (e.g. 140) can preventdiffusion from the interlayer conductors. For instance, the interlayerconductors can include highly diffusive materials, such as Cu (copper),that can cause reliability issues. The diffusion barrier layer (e.g.140) can include SiN (silicon nitride). The diffusion barrier layer(e.g. 140) can also stop etching of the first opening and the secondopening at top surfaces of the array of interlayer conductors. A thickerdiffusion barrier layer may increase capacitance of the RRAM cell, whilea thinner diffusion barrier layer may not be sufficient for preventingdiffusion from the interlayer conductors or may not stop etching of thefirst and second openings at top surfaces of the interlayer conductors.In one embodiment, the diffusion barrier layer (e.g. 140) can have athickness of about 30 nm (nanometer) within a range of 10 nm and 100 nm,to prevent diffusion from the interlayer conductors while not causingexcessive capacitance.

A first barrier layer (e.g. 180) is disposed conformal with andcontacting the metal oxide layer (e.g. 170) on the first interlayerconductor and surfaces of the first opening, including side and bottomsurfaces of the first opening. The first barrier layer (e.g. 180) caninclude a first layer of barrier material (e.g. 181) and a second layerof barrier material (e.g. 182) conformal with and contacting the firstlayer of barrier material. In one embodiment, each of the first layer ofbarrier material and the second layer of barrier material of the firstbarrier layer (e.g. 181 and 182) can have a thickness of about 10 nm(nanometer) within a range of 1 nm and 50 nm.

A second barrier layer can include the second layer of barrier material(e.g. 182) and is disposed conformal with and contacting a second topsurface (e.g. 132T) of the second interlayer conductor (e.g. 132) in thesecond opening and side and bottom surfaces of the second opening. Thesecond barrier layer has a thickness thinner than a thickness of thefirst barrier layer 180. In one embodiment, the second barrier layerincluding the second layer of barrier material (e.g. 182) can have athickness of about 10 nm (nanometer) within a range of 1 nm and 50 nm.

The first opening is filled with a conductive material (e.g. 185),contacting the first barrier layer (e.g. 180) in the first opening. Thesecond opening is filled with the conductive material (e.g. 185),contacting the second barrier layer in the second opening. The firstlayer of barrier material (e.g. 181) and the second layer of barriermaterial (e.g. 182) can comprise one or more layers of differentmaterials comprised of one or more elements selected from the groupconsisting of Ti, TiN, W, AlCu, TaN, Cu, Hf, Ta, Au, Pt, Ag, and othermetals which are CMOS compatible and do not alter the variableresistance properties of the metal oxide layer.

The first and second interlayer conductors (e.g. 131, 132) are connectedto first and second terminals (e.g. 111, 121) of an access devicerespectively. The first and second terminals of the access device aredisposed at a side of the dielectric layer opposite the first openingand the second opening.

The array of interlayer conductors extends through a dielectric layer(e.g. 120). The dielectric layer (e.g. 120) can include oxide materialssuch as PE (plasma enhanced) oxide, PETEOS (plasma enhanced tetraethylorthosilicate) oxide, LPTEOS low pressure tetraethyl orthosilicate)oxide, HDP (high density plasma) oxide, BPSG (borophosphosilicate glassfilm), PSG (phosphosilicate glass film), FSG (fluorosilicate glassfilm), low k materials and so on.

A first access line (not shown) can be electrically connected to themetal oxide layer, for example via the conductive material filled in thefirst opening, and act as a bit line of the memory cell. A second accessline (not shown) can be electrically connected to the second interlayerconductor, for example via the conductive material filled in the secondopening, and act as a source line of the memory cell. The first andsecond access lines can include one or more elements including Ti, W,Al, Cu, Pt, TaN, Hf, Ta and Ni. The first access line can include thesame material as the second access line, or a different material thanthe second access line. The conductive material (e.g. 185) filled in thefirst opening (e.g. 161) and the second opening (e.g. 162) can be formedat metal layer 1 (ML1), while the first and second access lines can beformed at metal levels 2, 3, 4 or n (ML2, ML3, ML4, or . . . MLn).Furthermore, the first and second access lines can be formed atdifferent metal levels. For example, the first access line can be formedat metal layer 3 (ML3), while the second access line can be formed atmetal layer 4 (ML4).

The access device can include a diode or a transistor. In an embodimentwhere the access device includes a transistor, a third access line (notshown) can be electrically connected to a gate terminal of thetransistor and act as a word line of the memory cell.

In operation, voltages applied between the first access line and firstinterlayer conductor 131 will cause current to flow between the firstaccess line and the first interlayer conductor 131 via the metal oxidelayer 170, and the first barrier layer 180. This current can induce aprogrammable change in electrical resistance of the metal oxide layer170, the electrical resistance indicating a data value stored in thememory cell 100. In some embodiments the metal oxide layer 170 of thememory cell 100 can store two or more bits of data.

FIGS. 2 through 8 illustrate example steps in manufacturing a memorycell as shown in FIG. 1. FIG. 2 illustrates results of forming adielectric layer (e.g. 120), forming an array of interlayer conductorsincluding first and second interlayer conductors (e.g. 131, 132)extending through the dielectric layer, and forming an insulating layer(e.g. 150) over the array of interlayer conductors, in a cross-sectionalview. In embodiments, a diffusion barrier layer (e.g. 140) can be formedbetween the insulating layer and the dielectric layer, and contactingtop surfaces (e.g. 131T, 132T) of the array of interlayer connectors, tostop etching of the first opening and the second opening at top surfacesof the array of interlayer conductors, and to protect the top surfacesof the interlayer conductors from oxidation. The dielectric layer caninclude silicon dioxide. The insulating layer will be patterned forforming top electrodes of memory cells. The first and second interlayerconductors are connected to first and second terminals of an accessdevice (e.g. 111, 112, FIG. 1), at a side of the dielectric layeropposite the insulating layer.

FIG. 3 illustrates results of etching the insulating layer to define afirst opening (e.g. 161) corresponding to the first interlayer conductor(e.g. 131) in the array, where the etching stops at the first topsurface (e.g. 131T) of the first interlayer conductor. In embodimentswhere the diffusion barrier layer is formed, the etching to define thefirst opening also etches through the diffusion barrier layer and stopsat top surfaces of the first interlayer conductor in the first opening.At this manufacturing step, an opening corresponding to the secondinterlayer conductor in the array of interlayer conductor is not presentin the insulating layer. For instance, when etching to define the firstopening, a first etch mask (e.g. 310), such as a photoresist mask, canbe used over the insulating layer, where the first etch mask has a maskregion corresponding to the second interlayer conductor and a spacedapart region corresponding to the first opening (e.g. 161).

FIG. 4 illustrates results of forming a metal oxide layer on the firsttop surface (e.g. 131T) of the first interlayer conductor in the firstopening. The metal oxide layer may be formed using various depositionand oxidation techniques, such as rapid thermal oxidation (RTO),photo-oxidation, direct plasma oxidation, down-stream plasma oxidation,sputtering, and reactive sputtering. For example, to oxidize W(tungsten) or Cu (copper) using RTO, the temperature can be from 200C to1100C in O₂ or O₂/N₂ ambient, and the process time can be from 5 secondsto 500 seconds, typically 30 seconds to 60 seconds. In embodiments wherethe first interlayer conductor includes W (tungsten), plasma oxidationcan result in a graded WxOy having concentrations of tungsten-oxygencompounds that have a distribution that varies with distance from thesurface exposed to oxidation. For instance, the metal oxide layer (e.g.170) can have a graded profile including WO₃, W₂O₅ and WO₂ such that theoxygen ratio in the metal oxide layer decreases in a direction from thefirst opening (e.g. 161) towards the first interlayer conductor (e.g.131). The metal oxide layer can extrude from the first top surface ofthe first interlayer conductor into the first opening due to volumeexpansion during forming the metal oxide layer.

In one implementation when the RTO oxidation technique is used, themetal oxide layer can have a thickness of about 50 nm (nanometer) withina range between 1 nm and 300 nm. In another implementation when theplasma oxidation technique is used, the metal oxide layer can have athickness of about 5 nm within a range of between 1 nm and 50 nm.

FIG. 5 illustrates results of depositing a first layer of barriermaterial (e.g. 181) in the first opening (e.g. 161), where the firstlayer of barrier material is conformal with and contacting the metaloxide layer on the first top surface of the first interlayer conductor,and conformal with and contacting side and bottom surfaces of the firstopening. In one embodiment, the first layer of barrier material (e.g.181) can have a thickness of about 10 nm (nanometer) within a range of 1nm and 50 nm. The first layer of barrier material (e.g. 181) cancomprise one or more layers of different materials comprised of one ormore elements selected from the group consisting of Ti, TiN, W, AlCu,TaN, Cu, Hf, Ta, Au, Pt, Ag, and other metals which are CMOS compatibleand do not alter the variable resistance properties of the metal oxidelayer. The first layer of barrier material can protect the metal oxidelayer from potential damage by subsequent manufacturing steps to formand then remove etch masks over the metal oxide layer, thus providingbetter interface between the metal oxide layer and the top electrode.

A minimum width of the first opening depends on the manufacturingtechnology. The first opening (e.g. 161) can have a width (e.g. W1)greater than a width (e.g. W2) of the first interlayer conductor (e.g.131). For instance, if the first interlayer conductor includes W(tungsten) and has a width of about 100 nm, then the first opening canhave a width greater than 120 nm.

FIG. 6 illustrates results of etching the insulating layer (e.g. 150) todefine a second opening (e.g. 162) corresponding to the secondinterlayer conductor (e.g. 132) in the array of interlayer conductors,where the etching stops at the second top surface (e.g. 132T) of thesecond interlayer conductor. This etching step to define the secondopening is subsequent to depositing the first layer of barrier materialas shown in FIG. 5, and etches through the first layer of barriermaterial (e.g. 181). In embodiments where the diffusion barrier layer isformed, the etching to define the second opening also etches through thediffusion barrier layer and stops at top surfaces of the secondinterlayer conductor in the second opening. In one implementation, thesecond opening (e.g. 162) can have a width matching the width of thefirst opening (e.g. 161).

In prior methods where a layer comprised of a metal oxide is formed onthe second top surface of the second interlayer conductor, the layercomprised of a metal oxide needs to be removed by processes such assputtering, and thus may cause contamination to side walls of the secondopening in the insulating layer. For instance, if the second interlayerconductor includes copper (Cu) and the metal oxide layer includes acopper oxide (CuOx), copper may be sputtered onto side walls of thesecond opening while the metal oxide layer is removed.

In embodiments of the present technology, since a layer comprised of ametal oxide is not present on the second top surface (e.g. 132T) of thesecond interlayer conductor (e.g. 132) and the etching stops at thesecond top surface (e.g. 132T) of the second interlayer conductor (e.g.132), such contamination to side walls of the second opening in theinsulating layer as may happen with the prior methods can be minimized.

At this manufacturing step to define the second opening, a second etchmask (e.g. 610), such as a photoresist mask, can be used over theinsulating layer (e.g. 150) and the first layer of barrier material(e.g. 181), where the second etch mask has a mask region correspondingto the first opening (e.g. 161) and a spaced apart region correspondingto the second opening (e.g. 162). Therefore the metal oxide layer (e.g.170) in the first opening is protected by the first layer of barriermaterial and the mask region in the second etch mask at thismanufacturing step.

FIG. 7 illustrates results of stripping the second etch mask (e.g. 610)as shown in FIG. 6, after the second opening (e.g. 162) is defined usingthe second etch mask. During the stripping, the metal oxide layer (e.g.170) in the first opening is protected by the first layer of barriermaterial (e.g. 181).

In preparation for depositing a second layer of barrier material, plasmacleaning can be used to remove impurities, contaminants, and nativeoxide from the second top surface (e.g. 132T) of the second interlayerconductor, through use of an energetic plasma created from gaseousspecies. For instance the gaseous species can include argon, and theplasma cleaning can etch a depth from about 1 nm to 20 nm. During theplasma cleaning, the metal oxide layer (e.g. 170) in the first openingis protected by the first layer of barrier material (e.g. 181).

FIG. 8 illustrates results of depositing a second layer of barriermaterial (e.g. 182) in the first opening and the second opening. Thesecond layer of barrier material is conformal with and contacting thefirst layer of barrier material (e.g. 181) in the first opening, andconformal with and contacting the second top surface (e.g. 132T) of thesecond interlayer conductor in the second opening and side and bottomsurfaces of the second opening. In one embodiment, the second layer ofbarrier material (e.g. 182) can have a thickness of about 10 nm(nanometer) within a range of 1 nm and 50 nm. The first layer of barriermaterial (e.g. 181) and the second layer of barrier material (e.g. 182)can comprise one or more layers of different materials comprised of oneor more elements selected from the group consisting of Ti, TiN, W, AlCu,TaN, Cu, Hf, Ta, Au, Pt, Ag, and other metals which are CMOS compatibleand do not alter the variable resistance properties of the metal oxidelayer.

A conductive material (e.g. 185) can be subsequently filled in the firstopening and the second opening. A first access line (not shown)electrically connected to the metal oxide layer can be formed, forexample via the conductive material filled in the first opening, and canact as a bit line for the memory cell. A second access line (not shown)electrically connected to the second interlayer conductor can be formed,for example via the conductive material filled in the second opening,and can act as a source line for the memory cell. The conductivematerial (e.g. 185) filled in the first opening (e.g. 161) and thesecond opening (e.g. 162) can be formed at metal layer 1 (ML1), whilethe first and second access lines can be formed at metal levels 2, 3, 4or n (ML2, ML3, ML4, or . . . MLn). Furthermore, the first and secondaccess lines can be formed at different metal levels. For example, thefirst access line can be formed at metal layer 3 (ML3), while the secondaccess line can be formed at metal layer 4 (ML4).

FIG. 9 shows a circuit diagram of a RRAM (Resistive random accessmemory) array in accordance with an embodiment. A RRAM array 900includes rows and columns of memory cells (e.g. 901, 902 and 903), whereeach memory cell includes a first transistor, a second transistor and amemory element (e.g. 901A, 901B and 901M) connected to a bit line. Thefirst and second transistors can be NMOS (N-type metal oxidesemiconductor) transistors. The memory element can include the metaloxide layer 170 as shown in FIG. 8. The memory cell can include thefirst layer of barrier material 181 and the second layer of barriermaterial 182 above the metal oxide layer 170 as shown in FIG. 1. Firstterminals of the first and second transistors in a memory cell areconnected to one end of the memory element in the memory cell. The threememory cells 901, 902 and 903 shown represent a small section of amemory array that can include thousands or millions of memory cells.

A plurality of first access lines (e.g. 911, 912 and 913) extends in afirst direction and is in electrical communication with a bit linedecoder (not shown) and the memory elements of the memory cells. Amemory element in a memory cell is connected to a first access line inthe plurality of first access lines at one end, and connected to firstterminals of the first and second transistors in the memory cell atanother end, via a first interlayer conductor (e.g. 941M) disposed belowthe memory element (e.g. 901M). A cross-sectional view of a firstinterlayer conductor is shown in FIG. 8 (e.g. 131). The plurality offirst access lines can act as bit lines.

A plurality of second access lines (e.g. 921, 922 and 923) extends inthe first direction, and terminates at a source line termination circuit(not shown). A second access line (e.g. 921) is in electricalcommunication with second terminals of the first and second transistors(e.g. 901A and 901B) in a memory cell, via second interlayer conductors(e.g. 941A and 941B). A cross-sectional view of a second interlayerconductor is shown in FIG. 8 (e.g. 132).The plurality of second accesslines can act as source lines.

A plurality of third access lines (e.g. 931-936) extends in a seconddirection orthogonal to the first direction. The third access lines arein electrical communication with a word line decoder (not shown), andcan act as word lines. Gate terminals of the first and secondtransistors (e.g. 901A and 901B) in the memory cells are connected torespective third access lines. The bit line decoder and the word linedecoder can include CMOS (complementary metal oxide semiconductor)circuitry.

FIG. 10 illustrates a simplified layout diagram of memory cells inaccordance with the embodiment shown in FIG. 9. Like elements in FIG. 10are referred to with like reference numerals in FIG. 9. The layout ofthe memory cells can be repeated in vertical and horizontal directions.For clarity, the insulation material is not shown, for example betweenthe first, second and third access lines.

The layout diagram illustrates first access lines 911 and 912 acting asbit lines (BL), second access lines 921 and 922 acting as source lines(SL), and third access lines 931, 932 and 933 acting as word lines (WL).In one implementation, the first access lines and the second accesslines can be disposed in a metal layer 1. The first, second and thirdaccess lines are connected to memory cells (e.g. 901 and 904), asdescribed in connection with FIG. 9. The memory cells include memoryelements (e.g. 901M) that can include the metal oxide layer 170 as shownin FIG. 8. The memory cells can include the first layer of barriermaterial 181, and the second layer of barrier material 182 above themetal oxide layer as shown in FIG. 1.

FIG. 11 shows a circuit diagram of a RRAM (Resistive random accessmemory) array in accordance with a second embodiment. A RRAM array 1100includes rows and columns of memory cells (e.g. 1101, 1102 and 1103),where each memory cell includes a first transistor, a second transistorand a memory element (e.g. 1101A, 1101B and 1101M). The first and secondtransistors can be NMOS (N-type metal oxide semiconductor) transistors.The memory cell can include the first layer of barrier material 181 andthe second layer of barrier material 182 above the memory element asshown in FIG. 1. The memory element can include the metal oxide layer170 as shown in FIG. 8. First terminals of the first and secondtransistors in a memory cell are connected to one end of the memoryelement in the memory cell, while second terminals of the first andsecond transistors in the memory cell are connected to a source line(e.g. 1121). The three memory cells 1101, 1102 and 1103 shown representa small section of a memory array that can include thousands or millionsof memory cells.

A plurality of first access lines (e.g. 1111, 1112 and 1113) extends ina first direction, and is in electrical communication with a bit linedecoder (not shown). The plurality of first access lines can act as bitlines. A plurality of second access lines (e.g. 1121, 1122 and 1123)extends in a second direction orthogonal to the first direction, andterminates at a source line termination circuit (not shown). Theplurality of second access lines can act as source lines.

The memory cells include first interlayer conductors (e.g. 1141M)disposed below the memory element (e.g. 1101M) connecting the memoryelement (e.g. 1101M) to first terminals of the first and secondtransistors (e.g. 1101A and 1101B), and second interlayer conductors(e.g. 1141A and 1141B) connecting second terminals of the first andsecond transistors to source lines (e.g. 1121). A cross-sectional viewof a first interlayer conductor and a second interlayer conductor isshown in FIG. 8 (e.g. 131 and 132).

A plurality of third access lines (e.g. 1131-1136) extends in the firstdirection. The third access lines are in electrical communication with aword line decoder (not shown), and can act as word lines. Gate terminalsof the first and second transistors (e.g. 1101A and 1101B) in the memorycells are connected to respective third access lines. The bit linedecoder and the word line decoder can include CMOS (complementary metaloxide semiconductor) circuitry.

FIG. 12 illustrates a simplified layout diagram of memory cells inaccordance with the second embodiment shown in FIG. 11. Like elements inFIG. 12 are referred to with like reference numerals in FIG. 11. Thelayout of the memory cells can be repeated in vertical and horizontaldirections. For clarity, the insulation material is not shown, forexample between the first, second and third access lines.

The layout diagram illustrates first access lines (e.g. 1111) acting asbit lines (BL), second access lines (e.g. 1121, 1122 and 1123) acting assource lines (SL), and third access lines (e.g. 1131, 1132 and 1133)acting as word lines (WL). In one implementation, the second accesslines can be disposed in a metal layer 1, and the first access lines canbe disposed in a metal layer 2 above the metal layer 1. The first,second and third access lines are connected to memory cells (e.g. 1101,1102 and 1103), as described in connection with FIG. 11. The memorycells include memory elements (e.g. 1101M) that can include the metaloxide layer 170 as shown in FIG. 8. The memory cells include the firstlayer of barrier material 181, and the second layer of barrier material182 above the metal oxide layer as shown in FIG. 1.

FIG. 13 shows a circuit diagram of a RRAM (Resistive random accessmemory) array in accordance with a third embodiment. A RRAM array 1300includes rows and columns of memory cells (e.g. 1301, 1302, 1303, 1304,1305, 1306, 1307 and 1308), where each memory cells includes atransistor and a memory element (e.g. 1301A and 1301M). The transistorcan be an NMOS (N-type metal oxide semiconductor) transistor. The memoryelement can include the metal oxide layer 170 in the memory cell asshown in FIG. 8. The memory cell can include the first layer of barriermaterial 181 and the second layer of barrier material 182 above themetal oxide layer 170 as shown in FIG. 1. A first terminal of thetransistor in a memory cell is connected to one end of the memoryelement in the memory cell. The memory cells shown represent a smallsection of a memory array that can include thousands or millions ofmemory cells.

A plurality of first access lines (e.g. 1311, 1312, 1313 and 1314)extends in a first direction, is in electrical communication with a bitline decoder (not shown), and is connected to a second end of the memoryelement opposite the end connected to the first terminal of thetransistor in the memory cell . The plurality of first access lines canact as bit lines. The memory cells can include first interlayerconductors (e.g. 1341M) disposed below the memory element (e.g. 1301M)connecting the memory element to first terminals of the transistors(e.g. 1301A). A cross-sectional view of a first interlayer conductor isshown in FIG. 8 (e.g. 131).

A plurality of second access lines (e.g. 1321, 1322, 1323 and 1324)extends in a second direction orthogonal to the first direction, andterminates at a source line termination circuit (not shown). Theplurality of second access lines can act as source lines. The memorycells can include second interlayer conductors (e.g. 1341) connectingsecond terminals of the transistors to source lines (e.g. 1321). Across-sectional view of a second interlayer conductor is shown in FIG. 8(e.g. 132).

A plurality of third access lines (e.g. 1331-1334) extends in the firstdirection. The third access lines are in electrical communication with aword line decoder (not shown), and can act as word lines. Gate terminalsof the transistors (e.g. 1301A) in the memory cells are connected torespective third access lines. The bit line decoder and the word linedecoder can include CMOS (complementary metal oxide semiconductor)circuitry.

FIG. 14 illustrates a simplified layout diagram of memory cells inaccordance with the third embodiment shown in FIG. 13. Like elements inFIG. 14 are referred to with like reference numerals in FIG. 13. Thelayout of the memory cells can be repeated in vertical and horizontaldirections. For clarity, the insulation material is not shown, forexample between the first, second and third access lines.

The layout diagram illustrates first access lines 1311 and 1312 actingas bit lines (BL), second access lines 1321, 1322 and 1323 acting assource lines (SL), and third access lines 1331 and 1332 acting as wordlines (WL). In one implementation, the second access lines can bedisposed in a metal layer 1, and the first access lines can be disposedin a metal layer 2 above the metal layer 1. The first, second and thirdaccess lines are connected to memory cells (e.g. 1301-1303 and1305-1306), as described in connection with FIG. 13. The memory cellsinclude memory elements (e.g. 1301M) that can include the metal oxidelayer 170 as shown in FIG. 8. The memory cells include the first layerof barrier material 181, and the second layer of barrier material 182above the metal oxide layer as shown in FIG. 1.

FIG. 15 shows a circuit diagram of a RRAM array in accordance with anembodiment using diodes as access devices. The memory array 1500includes a matrix of memory cells, a plurality of word lines (e.g. 1531,1532, 1533 and 1534) and a plurality of bit lines (e.g. 1511, 1512, 1513and 1514). Each of the memory cells (e.g. 1544) in the example memoryarray 1500 includes an access diode (e.g. 1544D) and a memory element(e.g. 1544M) in series between a corresponding word line (e.g. 1534) anda corresponding bit line (e.g. 1511). Each memory element iselectrically coupled to a corresponding access diode.

A memory cell in the memory array 1500 can include the first layer ofbarrier material 181 and the second layer of barrier material 182 abovethe memory element as shown in FIG. 1. The memory element in the memorycell includes the metal oxide layer 170 in the memory cell as shown inFIG. 8.

The plurality of bit lines including bit lines 1511, 1512, 1513 and 1514extends in parallel along a first direction. The bit lines are inelectrical communication with a bit line decoder 1510. Memory elementscan be connected between anodes or cathodes of diodes and bit lines. Forexample, the memory element 1544M is connected between the cathode ofdiode 1544D and the bit line 1511. The plurality of word lines includingword lines 1531, 1532, 1533 and 1534 extend in parallel along a seconddirection. The word lines 1531, 1532, 1533 and 1534 are in electricalcommunication with a word line decoder 1530. Cathodes or anodes ofdiodes may be connected to word lines. For example, the anode of diode1544D is connected to a word line 1534. The bit line decoder and theword line decoder can include CMOS (complementary metal oxidesemiconductor) circuitry. It should be noted that the sixteen memorycells in FIG. 15 are shown for convenience of discussion but, inpractice, a memory array may comprise thousands or millions of suchmemory cells.

FIG. 16 illustrates a simplified layout diagram of memory cells inaccordance with the embodiment using diodes as access devices shown inFIG. 15. Like elements in FIG. 16 are referred to with like referencenumerals in FIG. 15. The layout of the memory cells can be repeated invertical and horizontal directions. For clarity, the insulation materialis not shown, for example between the first and second access lines.

The layout diagram illustrates first access lines 1511, 1512, 1513 and1514 acting as bit lines (BL), and second access lines 1531, 1532, 1533and 1534 acting as word lines (WL). The second access lines can includeactive areas for the diodes (e.g. 1544D) in the memory cells, and can beconnected to contacts (e.g. 1551, 1552, 1553 and 1554) for word linepickup. In one implementation, the bit lines can be disposed in a metallayer 1, above the word lines that can include polysilicon. The firstand second access lines are connected to memory cells (e.g. 1544), asdescribed in connection with FIG. 15. The memory cells include memoryelements (e.g. 1541M, 1542M, 1543M and 1544M) that can include the metaloxide layer 170 as shown in FIG. 8. The memory cells can include thefirst layer of barrier material 181, and the second layer of barriermaterial 182 above the memory elements as shown in FIG. 1.

FIG. 17 illustrates a simplified flowchart of an embodiment of a methodfor manufacturing a memory device. At Step 1701, an insulating layer isformed over an array of interlayer conductors. A diffusion barrier layercan be formed between top surfaces of the array of interlayer conductorsand the insulating layer, and contacting the top surfaces. At Step 1702,the insulating layer is etched to define a first opening correspondingto a first interlayer conductor in the array, where the etching stops ata first top surface of the first interlayer conductor. When etching todefine the first opening, a first etch mask can be used over theinsulating layer, where the first etch mask has a mask regioncorresponding to the second opening and a spaced apart regioncorresponding to the first opening.

At Step 1703, a metal oxide layer is formed on the first top surface ofthe first interlayer conductor in the first opening. The metal oxidelayer can be characterized by having a programmable resistance. At Step1704, a first layer of barrier material is deposited conformal with andcontacting the metal oxide layer on the first interlayer conductor andsurfaces of the first opening. The first layer of barrier material canprotect the metal oxide layer from potential damage by subsequentmanufacturing steps to form and then remove etch masks over the metaloxide layer, thus providing better interface between the metal oxidelayer and the top electrode.

At Step 1705, subsequent to depositing the first layer of barriermaterial, the insulating layer is etched to define a second openingcorresponding to a second interlayer conductor in the array, where theetching stops at a second top surface of the second interlayerconductor. When etching to define the second opening, a second etch maskcan be used over the insulating layer, where the second etch mask has amask region corresponding to the first opening and a spaced apart regioncorresponding to the second opening. At Step 1706, a second layer ofbarrier material is deposited conformal with and contacting the firstlayer of barrier material in the first opening. The second layer ofbarrier material can also be deposited conformal with and contacting thesecond top surface of the second interlayer conductor in the secondopening and surfaces of the second opening, for example at the samestep.

At Step 1707, the first opening is filled with a conductive material.The second opening can also be filled with the conductive material, forexample at the same step, where a layer comprised of a metal oxide isnot present between the second top surface and the second layer ofbarrier material. The first opening can have a width greater than awidth of the first interlayer connector.

The first and second interlayer conductors can be connected to first andsecond terminals of an access device respectively. An access device caninclude a diode or a transistor. An array of access devices can beformed coupled to the array of interlayer conductors including the firstand second interlayer conductors.

It will be understood that the memory array is not limited to the arrayconfiguration illustrated in FIG. 12 and additional array configurationscan also be used with memory cells including a top electrode layer asdisclosed above. Additionally, instead of MOS transistors, bipolartransistors or diodes may be used as access devices in some embodiments.

While the present technology is disclosed by reference to the preferredembodiments and examples detailed above, it is understood that theseexamples are intended in an illustrative rather than in a limitingsense. It is contemplated that modifications and combinations willreadily occur to those skilled in the art, which modifications andcombinations will be within the spirit of the technology and the scopeof the following claims.

1. A method of manufacturing a memory, comprising: forming an insulatinglayer over an array of interlayer conductors; etching the insulatinglayer to define a first opening corresponding to a first interlayerconductor in the array, stopping at a first top surface of the firstinterlayer conductor; forming a metal oxide layer on the first topsurface of the first interlayer conductor in the first opening;depositing a first layer of barrier material conformal with andcontacting the metal oxide layer on the first interlayer conductor andsurfaces of the first opening, wherein the first opening has a widthgreater than a width of the first interlayer conductor; etching theinsulating layer to define a second opening corresponding to a secondinterlayer conductor in the array, stopping at a second top surface ofthe second interlayer conductor, subsequent to said depositing the firstlayer of barrier material; depositing a second layer of barrier materialconformal with and contacting the first layer of barrier material in thefirst opening; and filling the first opening with a conductive material,wherein the first and second interlayer conductors are connected tofirst and second terminals of an access device respectively.
 2. Themethod of claim 1, comprising: forming a diffusion barrier layer betweentop surfaces of the array of interlayer conductors and the insulatinglayer and contacting the top surfaces.
 3. The method of claim 1, saidetching to define the first opening comprising: using a first etch maskover the insulating layer, the first etch mask having a mask regioncorresponding to the second opening and a spaced apart regioncorresponding to the first opening.
 4. The method of claim 1, saidetching to define a second opening comprising: using a second etch maskover the insulating layer, the second etch mask having a mask regioncorresponding to the first opening and a spaced apart regioncorresponding to the second opening.
 5. The method of claim 1, saiddepositing the second layer of barrier material comprising: depositingthe second layer of barrier material conformal with and contacting thesecond top surface of the second interlayer conductor in the secondopening and surfaces of the second opening; and filling the secondopening with the conductive material.
 6. The method of claim 1,comprising: forming a first access line electrically connected to themetal oxide layer; and forming a second access line electricallyconnected to the second interlayer conductor.
 7. The method of claim 1,comprising: forming an array of access devices coupled to the array ofinterlayer conductors, and including the first mentioned access device.8. The method of claim 1, wherein the first mentioned access deviceincludes a diode.
 9. The method of claim 1, wherein the first mentionedaccess device includes a transistor, comprising: forming a third accessline electrically connected to a gate terminal of the transistor. 10.The method of claim 1, wherein the metal oxide layer is characterized byhaving a programmable resistance.
 11. The method of claim 1, wherein thefirst interlayer connector consists essentially of a metal, and themetal oxide layer comprises an oxide of the metal.
 12. The method ofclaim 1, wherein the first interlayer connector consists essentially ofa transition metal, and the metal oxide layer comprises an oxide of thetransition metal.
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